Off-state leakage, also referred to as static power, is the current that leaks through transistors even when they are turned off. Dynamic power, which arises from short circuit dissipation and the switching power consumed by the repeated charge and discharge of the load capacitances of the hundreds of millions of transistor gates in today's chips, has been a significant source of power consumption. However, as the semiconductor industry moves into the nanometer technologies, static power consumption elevates to unacceptable levels.
Indeed, static power consumption is a serious problem for electronic circuits fabricated using deep submicron technologies. A consequence of static power consumption is that an integrated circuit continues to “leak” power even if it is in standby mode. For portable devices such as cell phones, PDAs, and laptops, static power consumption needs to be reduced to prolong battery lifetime. Considering the wide range of applications offered by portable devices, as well as the huge market depending on these devices, the reduction of static power has been identified as a major goal for industry.
The exponential increase of the sub-threshold leakage current in the deep submicron technologies is a large contributor to the increased static power. The increased sub-threshold leakage current is caused by the reduction of the supply voltage, which consequently leads to the reduction of the threshold voltage (Vth) of the devices.
Many techniques have been presented for tackling the very high leakage power dissipated in these circuits. Some techniques try to reduce the leakage power during the active mode of the circuit operation while other techniques try to reduce the leakage power consumed during the periods of circuit inactivity.
In the first case, the circuit is typically partitioned into two regions: a high performance region and a low performance region. For the high performance region, which is used for performance-critical parts of the circuit, the cells contain low-threshold devices with high performance characteristics, but also high leakage power. For the low performance region, which is used in the high-slack parts of the design, the cells contain high-threshold devices with less leaky but also low-speed cells. By using the two types of cells, the overall (normal as well as standby mode) static power is reduced without any significant performance degradation.
In the second case, the target is to further reduce the leakage power during long periods of inactivity of the circuit operation. Many digital cores (e.g., processors) remain idle for long periods during their normal operation. For such cases, further improvements can be achieved using power gating techniques, which turn off the cores during long idle periods. By turning off the cores during long idle periods, the power consumed during these periods of inactivity is significantly reduced and may be almost eliminated. To turn off the cores, additional power-gating transistors are provided between the core under test and the power rail or the ground rail, which turn on and/or turn off the cores. By turning off the cores during idle periods, greater power savings can be accomplished at the circuit.
A typical power switch consists of a footer transistor connected between the core and the ground rail. When the footer is “on” the core operates according to its normal operation. When it is “off” (i.e. during idle mode) the virtual ground rail charges to a voltage level close to the power supply, thus reducing the leakage power consumed. In order not to affect the circuit performance during normal operation of the core, the footer transistor must comprise a strong driver, and thus its ratio W/L must be very large. In practice, instead of using a very large transistor, many small parallel transistors are used as the power switch.
Although the power savings using these power switches shows promise for deep submicron technologies, there remains a need for techniques and designs for additional power savings.
For example, even though the power savings using the power switches are high, the time required for recovering from the idle mode tends to prohibit the use of the power switches during short periods of inactivity. The short periods of inactivity include wake-up time, which is the time required to completely discharge the virtual ground rail.
Thus, there continues to be a need in the art for improved techniques and designs to reduce static power consumption.